/**
  ******************************************************************************
  * @file    gt32f030_adc.c
  * @author  GT Application Team
  * @version V1.0.0
  * @date    03-January-2025
  *       
  ******************************************************************************
  * @attention
  *
  * <h2><center>&copy; COPYRIGHT 2022 Giantec Semicondutor Inc</center></h2>
  *
  *             http://www.giantec-semi.com/
  *
  * Unless required by applicable law or agreed to in writing, software 
  * distributed under the License is distributed on an "AS IS" BASIS, 
  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  * See the License for the specific language governing permissions and
  * limitations under the License.
  *
  ******************************************************************************
  */

/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __GT32F030_ADC_H
#define __GT32F030_ADC_H	 

#ifdef __cplusplus
 extern "C" {
#endif
#include "gt32f030.h"

/** @addtogroup GT32F030_StdPeriph_Driver
  * @{
  */

/** @addtogroup ADC
  * @{
  */ 

/* Exported macro ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/

/** @defgroup ADC_Exported_Constants
  * @{
  */

#define IS_ADC_CLKPRESCALE(PRESCALE) (PRESCALE < 0xFF)
#define IS_ADC_PWONDLY(PWONDLY)      (PWONDLY < 0x3FF)
#define IS_ADC_DISCCONVLENGTH_REG(LENGTH) ((LENGTH >= 0x1)&&(LENGTH <= 0x7))
#define IS_ADC_DISCCONVLENGTH_INJ(LENGTH) ((LENGTH >= 0x1)&&(LENGTH <= 0x4))
#define IS_ADC_HIGHTHRESHOLD(THRESHOLD)    (THRESHOLD <= 0x3ff)
#define IS_ADC_LOWTHRESHOLD(THRESHOLD)     (THRESHOLD <= 0x3ff)
#define IS_ADC_ACCLENGTH(ACCLENGTH) ((ACCLENGTH >=1)&&(ACCLENGTH <= 0x100))
#define IS_ADC_SQRLENGTH(LENGTH)  ((LENGTH >=1) &&(LENGTH <= 12))
#define IS_ADC_JSQRLENGTH(LENGTH) ((LENGTH >=1) &&(LENGTH <= 4))


///** @defgroup ADC_Vref_selection_define 
//  * @{
//  */
//#define ADC_Vref_Inter1p8          ((uint32_t)0x00000000)
//#define ADC_Vref_Inter2p4          ((uint32_t)0x00010000)
//#define ADC_Vref_VDD               ((uint32_t)0x00000100)
//#define ADC_Vref_External          ((uint32_t)0x00000200)
//#define IS_ADC_VERF(VERF) (((VERF) == ADC_Vref_Inter1p8) || \
//                           ((VERF) == ADC_Vref_Inter2p4) || \
//                           ((VERF) == ADC_Vref_VDD)      || \
//                           ((VERF) == ADC_Vref_External))
/**
  * @}
  */													 

/** @defgroup ADC_SampChnCycle_define 
  * @{
  */ 
typedef enum
{
	ADC_SampChnCycle_2Clk = 0x0,
	ADC_SampChnCycle_4Clk = 0x1,
	ADC_SampChnCycle_8Clk = 0x2,
	ADC_SampChnCycle_32Clk = 0x3,
	ADC_SampChnCycle_64Clk = 0x4,
	ADC_SampChnCycle_128Clk = 0x5,
	ADC_SampChnCycle_256Clk = 0x6,
	ADC_SampChnCycle_512Clk = 0x7,
}ADCSampChnCycle_Typedef;
#define IS_ADC_SAMPCLK(SAMPCLK) (((SAMPCLK) == ADC_SampChnCycle_2Clk) || \
                                 ((SAMPCLK) == ADC_SampChnCycle_4Clk) || \
                                 ((SAMPCLK) == ADC_SampChnCycle_8Clk) || \
                                 ((SAMPCLK) == ADC_SampChnCycle_32Clk) || \
                                 ((SAMPCLK) == ADC_SampChnCycle_64Clk) || \
                                 ((SAMPCLK) == ADC_SampChnCycle_128Clk) || \
                                 ((SAMPCLK) == ADC_SampChnCycle_256Clk) || \
                                 ((SAMPCLK) == ADC_SampChnCycle_512Clk))
/**
  * @}
  */


/** @defgroup ADC_converter_Source_define 
  * @{
  */
typedef enum
{
	ADC_ConvGroup_Regular = 0x0,
	ADC_ConvGroup_Inject  = 0x1,	
}ADCConvGroup_Typedef;
#define IS_ADC_CONVGROUP(CONVGROUP) (((CONVGROUP) == ADC_ConvGroup_Regular) || \
                                     ((CONVGROUP) == ADC_ConvGroup_Inject)) 

#define ADC_ChnSource0            ((uint8_t)0x00)
#define ADC_ChnSource1            ((uint8_t)0x01)
#define ADC_ChnSource2            ((uint8_t)0x02)
#define ADC_ChnSource3            ((uint8_t)0x03)
#define ADC_ChnSource4            ((uint8_t)0x04)
#define ADC_ChnSource5            ((uint8_t)0x05)
#define ADC_ChnSource6            ((uint8_t)0x06)
#define ADC_ChnSource7            ((uint8_t)0x07)
#define ADC_ChnSource8            ((uint8_t)0x08)
#define ADC_ChnSource9            ((uint8_t)0x09)
#define ADC_ChnSource10           ((uint8_t)0x0A)
#define ADC_ChnSource11           ((uint8_t)0x0B)
#define IS_ADC_CHNSRC(SRC) ((SRC) <= 0x0B)

#define ADC_Regular_Sequ0            ((uint8_t)0x00)
#define ADC_Regular_Sequ1            ((uint8_t)0x01)
#define ADC_Regular_Sequ2            ((uint8_t)0x02)
#define ADC_Regular_Sequ3            ((uint8_t)0x03)
#define ADC_Regular_Sequ4            ((uint8_t)0x04)
#define ADC_Regular_Sequ5            ((uint8_t)0x05)
#define ADC_Regular_Sequ6            ((uint8_t)0x06)
#define ADC_Regular_Sequ7            ((uint8_t)0x07)
#define ADC_Regular_Sequ8            ((uint8_t)0x08)
#define ADC_Regular_Sequ9            ((uint8_t)0x09)
#define ADC_Regular_Sequ10           ((uint8_t)0x0A)
#define ADC_Regular_Sequ11           ((uint8_t)0x0B)
#define IS_ADC_SEQUSRC(SQR) ((SQR) <= 0x0B) 
	 
#define ADC_Inject_Sequ0            ((uint8_t)0x00)
#define ADC_Inject_Sequ1            ((uint8_t)0x01)
#define ADC_Inject_Sequ2            ((uint8_t)0x02)
#define ADC_Inject_Sequ3            ((uint8_t)0x03)
#define IS_ADC_JSEQUSRC(JSQR) ((JSQR) <= 0x03) 

typedef enum
{
	ADC_ConvData_InJect1  = 0x0,
	ADC_ConvData_InJect2  = 0x1,
	ADC_ConvData_InJect3  = 0x2,
	ADC_ConvData_InJect4  = 0x3,
  ADC_ConvData_Regular  = 0x4,	
	ADC_ConvData_ACC      = 0x5,	
}ADCConvData_Typedef;
#define IS_ADC_CONVDATA(CONVDATA) (((CONVDATA) == ADC_ConvData_InJect1) || \
                                   ((CONVDATA) == ADC_ConvData_InJect2) || \
                                   ((CONVDATA) == ADC_ConvData_InJect3) || \
                                   ((CONVDATA) == ADC_ConvData_InJect4) || \
                                   ((CONVDATA) == ADC_ConvData_Regular) || \
                                   ((CONVDATA) == ADC_ConvData_ACC)) 
/**
  * @}
  */
	
	

/** @defgroup ADC_IT_FLAG_define 
  * @{
  */
#define ADC_JSQRAWD      BIT0
#define ADC_SQRAWD       BIT1
#define ADC_JEOC         BIT2
#define ADC_EOC          BIT3
#define ADC_JSTART       BIT4
#define ADC_START        BIT5
#define ADC_ACC          BIT6
#define ADC_OVF          BIT7
#define ADC_VLD          BIT8
#define IS_ADC_IT(IT)     (((IT) == ADC_JSQRAWD)  ||  \
                           ((IT) == ADC_SQRAWD)   ||  \
                           ((IT) == ADC_JEOC)     ||  \
											     ((IT) == ADC_EOC)      ||  \
                           ((IT) == ADC_ACC)      ||  \
											     ((IT) == ADC_OVF)      ||  \
													 ((IT) == ADC_VLD) )													

#define IS_ADC_STS(STS)   (((STS) == ADC_JSQRAWD)  ||  \
                           ((STS) == ADC_SQRAWD)   ||  \
                           ((STS) == ADC_JEOC)     ||  \
											     ((STS) == ADC_EOC)      ||  \
													 ((STS) == ADC_JSTART)   ||  \
											     ((STS) == ADC_START)    ||  \
                           ((STS) == ADC_ACC)      ||  \
											     ((STS) == ADC_OVF)      ||  \
											     ((STS) == ADC_VLD) )
/**
  * @}
  */													 
													 


/** @defgroup ADC_External_Trigger_define 
  * @{
  */
typedef enum
{
	ADC_ExtTrgEdge_Disable  = 0x0,
	ADC_ExtTrgEdge_Rise     = 0x1,
	ADC_ExtTrgEdge_Fall     = 0x2,
	ADC_ExtTrgEdge_Both     = 0x3	
}ADCExtTrgEdge_Typedef;

#define IS_ADC_EXTTRGEDGE(EDGE)  (((EDGE) == ADC_ExtTrgEdge_Disable) || \
                                  ((EDGE) == ADC_ExtTrgEdge_Rise)    || \
                                  ((EDGE) == ADC_ExtTrgEdge_Fall)    || \
                                  ((EDGE) == ADC_ExtTrgEdge_Both))
typedef enum
{
	ADC_ExtTrgSrc_None         = 0x00,	
	ADC_ExtTrgSrc_IRQTim10     = 0x01,   //000001 irq_timer10
	ADC_ExtTrgSrc_IRQTim11     = 0x02,   //000010 irq_timer11
	ADC_ExtTrgSrc_IRQTim1      = 0x03,   //000011 irq_pwm
	ADC_ExtTrgSrc_IRQLpTim     = 0x04,   //000100 irq_lptimer
	ADC_ExtTrgSrc_IRQTim1Trgo  = 0x05,   //000101 tim1_trgo
	ADC_ExtTrgSrc_IRQTim2Trgo  = 0x06,   //000110 tim2_trgo
	ADC_ExtTrgSrc_IRQTim2      = 0x07,   //000111 irq_tim2
	ADC_ExtTrgSrc_IRQUart0     = 0x08,   //001000 irq_uart0
																	 //001001
	ADC_ExtTrgSrc_IRQUart1     = 0x0A, //001010 irq_lpuart
	ADC_ExtTrgSrc_IRQVC        = 0x0B, //001011 irq_vc
																	 //001100
	ADC_ExtTrgSrc_IRQRTC       = 0x0D, //001101 irq_rtc
	ADC_ExtTrgSrc_IRQPCA       = 0x0E, //001110 irq_pca
	ADC_ExtTrgSrc_IRQSPI       = 0x0F, //001111 irq_spi0
	ADC_ExtTrgSrc_PA0          = 0x10,  //010000 gpioa_int[0]
	ADC_ExtTrgSrc_PA1          = 0x11,  //010001 gpioa_int[1]
	ADC_ExtTrgSrc_PA2          = 0x12,  //010010 gpioa_int[2]
	ADC_ExtTrgSrc_PA3          = 0x13,  //010011 gpioa_int[3]
	ADC_ExtTrgSrc_PB0          = 0x14,  //010100 gpiob_int[0]
	ADC_ExtTrgSrc_PB1          = 0x15,  //010101 gpiob_int[1]
	ADC_ExtTrgSrc_PB2          = 0x16,  //010110 gpiob_int[2]
	ADC_ExtTrgSrc_PB3          = 0x17,  //010111 gpiob_int[3]
	ADC_ExtTrgSrc_PB4          = 0x18,  //011000 gpiob_int[4]
	ADC_ExtTrgSrc_PB5          = 0x19,  //011001 gpiob_int[5]
	ADC_ExtTrgSrc_PB6          = 0x1A,  //011010 gpiob_int[6]
	ADC_ExtTrgSrc_PB7          = 0x1B,  //011011 gpiob_int[7]
														         //011100
	ADC_ExtTrgSrc_PC1          = 0x1D,  //011101 gpioc_int[1]
	ADC_ExtTrgSrc_PC2          = 0x1E,  //011110 gpioc_int[2]
	ADC_ExtTrgSrc_PC3          = 0x1F,  //011111 gpioc_int[3]
	ADC_ExtTrgSrc_PC4          = 0x20,  //100000 gpioc_int[4]
	ADC_ExtTrgSrc_PC5          = 0x21,  //100001 gpioc_int[5]
	ADC_ExtTrgSrc_PC6          = 0x22,  //100010 gpioc_int[6]
	ADC_ExtTrgSrc_PC7          = 0x23,  //100011 gpioc_int[7]
	ADC_ExtTrgSrc_PD0          = 0x24,  //100100 gpiod_int[0]
	ADC_ExtTrgSrc_PD1          = 0x25,  //100101 gpiod_int[1]
	ADC_ExtTrgSrc_PD2          = 0x26,  //100110 gpiod_int[2]
	ADC_ExtTrgSrc_PD3          = 0x27,  //100111 gpiod_int[3]
	ADC_ExtTrgSrc_PD4          = 0x28,  //101000 gpiod_int[4]
	ADC_ExtTrgSrc_PD5          = 0x29,  //101000 gpiod_int[4]
	ADC_ExtTrgSrc_PD6          = 0x2A,  //101000 gpiod_int[4]
	ADC_ExtTrgSrc_PD7          = 0x2B,  //101000 gpiod_int[4]
	ADC_ExtTrgSrc_PE5          = 0x2C,  //101000 gpiod_int[4]
	ADC_ExtTrgSrc_PF4          = 0x2D,  //101000 gpiod_int[4]
}ADCExtTrgSrc_Typedef;
#define IS_ADC_EXTTRGSRC(SRC) (((SRC) < 0x2D) && ((SRC) != 0x09) && ((SRC) != 0x0C) && ((SRC) != 0x1C))
/**
  * @}
  */	



/**
  * @}
  */

/* Exported types ------------------------------------------------------------*/
/** 
  * @brief   ADC Analog Watchdog Threshold structure definition  
  */
typedef struct
{        
  ADCConvGroup_Typedef  ADC_ConvGroup;
  unsigned int    ADC_WdgThreshold_High;
	unsigned int    ADC_WdgThreshold_Low;	
}ADCWdgThreshold_Typedef;

/** 
  * @brief   ADC Sample Channel structure definition  
  */
typedef struct
{        
  unsigned int             ADC_SampChn;	
  ADCSampChnCycle_Typedef  ADC_SampChnCycle;         
  FunctionalState          ADC_SampChnAWD;            
  FunctionalState          ADC_SampChnACCCmd; 
  unsigned int             ADC_SampChnACCLength;
}ADC_SampChnCfgTypeDef;

/** 
  * @brief   ADC Discontinue configuration structure definition  
  */
typedef struct
{                   
  ADCConvGroup_Typedef  ADC_ConvGroup;         
  FunctionalState       ADC_DiscConvModeCmd;            
  unsigned int          ADC_DiscConvLength;               
}ADC_DiscontinueCfgTypeDef;

/** 
  * @brief   ADC External Trigger structure definition  
  */
typedef struct
{                    
  ADCConvGroup_Typedef  ADC_ConvGroup;         
  ADCExtTrgEdge_Typedef ADC_ExtTrgEdge;           
  ADCExtTrgSrc_Typedef  ADC_ExtTrgSrc;               
}ADC_ExtTrgInitTypeDef;

/** 
  * @brief   GPIO Init structure definition  
  */
typedef struct
{
  FunctionalState  ADC_InputBuf;	  
	unsigned int     ADC_ClkPrescale; 
  unsigned int     ADC_PowerOnDelay;	
}ADC_InitTypeDef;




/* Exported functions --------------------------------------------------------*/  
void ADC_DeInit(void);
void ADC_Init(ADC_InitTypeDef* ADC_InitStruct);
void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);

void ADC_SampChnConfig(ADC_SampChnCfgTypeDef* ADC_SampChnCfgStruct);
void ADC_ScanModeCmd(FunctionalState NewState);
void ADC_ContinueModeCmd(FunctionalState NewState);
void ADC_DMACmd(FunctionalState NewState);
void ADC_JAutoModeCmd(FunctionalState NewState);
void ADC_SQRnChnConfig(unsigned int SEQUn,unsigned int  ADC_Chn);
void ADC_JSQRnChnConfig(unsigned int SEQUn,unsigned int  ADC_Chn);
void ADC_SQRLengthConfig(unsigned int SqrLength);
void ADC_JSQRLengthConfig(unsigned int JSqrLength);
void ADC_WatchdogThresholdConfig(ADCWdgThreshold_Typedef* ADCWdgThresholdStruct);
void ADC_ExtTriggerConfig(ADC_ExtTrgInitTypeDef* ADC_ExtTrgInitStruct);
void ADC_DiscontinueConfig(ADC_DiscontinueCfgTypeDef* ADC_DiscCfgStruct);
void ADC_PowerOnCmd(FunctionalState NewState);
void ADC_SWStartCmd(ADCConvGroup_Typedef convgroup,FunctionalState NewState);
unsigned int ADC_GetData(unsigned int ADC_ConvData);
unsigned int ADC_GetConversionValue(unsigned int ADC_ConvData);

void ADC_ITConfig(unsigned int ADC_IT, FunctionalState NewState);
ITStatus ADC_GetIT(unsigned int ADC_IT);
void ADC_ClearIT(unsigned int ADC_IT);
FlagStatus ADC_GetFlagStatus(unsigned int ADC_Flag);
void ADC_ClearSR(unsigned int ADC_FLAG);
#ifdef __cplusplus
}
#endif

#endif /* __GT32F030_ADC_H */

/**
  * @}
  */ 

/**
  * @}
  */ 

/************************ (C) COPYRIGHT Giantec Semicondutor Inc *****END OF FILE****/

